NIKHEF Digitizer Device Driver

From the four input channels of the digitizer, signals are first digitized by 200 MHz ADCs. The ADCs are then read out by an Altera FPGA, which also handles triggering, filtering, and timestamping. The FPGA then communicates with the CPU via a 4-bit, 40 MHz MSL (Mobile Scalable Link) bus.

Software readout of the FPGA over the MSL bus is facilitated by a custom Linux device driver. The driver creates a char device, /dev/scope, for read/write to the FPGA. Command structures and data formats can be found on Thei Wijnen's page.

The device driver code can be checked out of the maxima_daq SVN project on merum (talk to me for an account), or the pre-compiled kernel modules can be downloaded here (for kernel 2.6.27.48).

Latest, v110414.ko:
msl_110414_vpac1.ko (2.6.27.48-vpac1 kernel / VPAC1 cards)
msl_110414_vpac2.ko (2.6.27.48-vpac2 kernel / VPAC2 cards)
no DMA, v090819: msl_090819.ko

Changelog:

110414: Safer DMA interrupt disabling / re-enabling on driver close and re-open.
100728: Fix false positive in MSL watchdog code.
100621: Fix for writes larger than 64B.
100614: Workaround / partial fix for MSL fault condition. PXA270 likely has a bug in the DMA controller that results in an illegal MSL status (FIFO empty but EOM indicated). Reducing DMA burst size to 8 reduces the frequency of this happening. The driver also monitors for this condition and issues an emergency reboot when detected.